1. Field of the Invention
This invention relates to a method of transferring data in a computer system while optimizing wiring, latency, design re-use, RAS, and debugability with dual pipe and dual dataflow communication and controls for doublewords.
2. Description of Background
This invention relates to in-band computer system maintenance operations. In computers, particularly on High-end servers, there are maintenance and support operations that are continuously occurring. For instance, polling for errors, instrumentation of events, communications to optimize configuration settings, recovery, data movement, workload redistribution, etc. Most often, these operations require an infrastructure for communication. However, they don't always require fast turn-around times or high bandwidth. However, there are other operations, like maintaining consistent time-of-day, where minimized latency is key. Since these operations often require the use of microcode for best programmability, operations can be retried in the case of failure. However, detecting errors in the system is important. Failure to execute some operation in the right sequence can cause data integrity errors. So, it is also important that the mechanism for data and control transfer has adequate RAS features (error detection and ability to retry operations).
Some of the prior art in this field had entirely serial structures. These structures allowed for large address spaces and large data fields. This is done with large serializers, so the data space comes with a cost in time. While optimized for wiring resources, these designs do not have the minimized latency needed for other operations, like time-of-day. Also, isolation of failures was difficult without some additional features.
Other prior art used address and control buses to do minimal maintenance operations. The problem with these systems is they did not have the ability to use a large maintenance address and data space. They also did not have much data protection on all operations.
One aspect of the invention is to use the existing data and control structure of the cache and dataflow in the system. This allows the advantage of high-RAS data and address protection. Another aspect is to separate operations into a fast queue and a slow queue. So, all the operations that need quick turn-around times (like time-of-day operations) do not get behind operations that can tolerate slow turn-around times and which often take longer.
Another aspect of the invention is to use parallel satellite controls for the fast queue while using cheaper, slow, serial satellite controls for the slow queue.
Both fast and slow queues make use of common building blocks. These building blocks are used in the data flow (where there is a converter from parallel, 64-bit data plus ECC to 16-bit sequenced data and conversion the other way as well).
Another aspect of the invention is how the fast engine and the slow engine use the same overall parallel sequence and components. They both handle conversion from/to ECC and parity in both directions. They also have address, controls, and data as well as packet checking and error reporting.